The invention relates to an analog-to-digital converters (ADCs), and in particular, to a series-connected A/D converter, such as an asynchronous A/D converter, a successive-approximation A/D converter and a cyclic comparison A/D converter as presented in this invention.
Analog-to-digital conversion is a vital device for a lot of applications, because most signals are analog in nature and have to be digitized for interpretation and digital signal processing. Traditionally, analog-to-digital converters (ADCs) are applied to digitize the signal, where the ADC is required to possess the characteristic of having a high resolution, wide dynamic range, high conversion speed, and low power consumption.
Flash ADCs perform well in term of conversion speed, because all bits of the digital word are determined simultaneously. However, flash ADCs are usually constructed to have a short conversion word length (usually less than 8 bits), and thus poor resolution, because high resolution flash ADCs occupy a large silicon area, which makes them less favorable in high resolution application.
Successive-approximation ADCs are frequently used in medium-to-high-resolution applications, where the conversion word lengths are usually in the range of 8 to 16 bits. This is because successive-approximation ADCs can achieve reasonable conversion rate with low power consumption.
Successive-approximation ADC samples an analog input and compares it to the output of a digital-to-analog converter (DAC), where the output of the DAC is sequentially determined by a series of comparison between the input to a number of references until the difference between the DAC output and analog input is smaller than the conversion resolution. Successive-approximation ADCs systematically evaluate the analog input signal in N steps to produce an N-bit digital word. The determination of the digital word begins with the most significant bit (MSB) and progressively to the least significant bit (LSB).
One of the disadvantages of successive-approximation ADCs is that each bit must be determined sequentially and in synchronization with the clock signal. As a result, O(N) clocks cycles (i.e., number of clock cycles is with the order of N) are required to convert an analog signal to a N-bit digital signal, where only O(1) clock cycle is required in flash ADC. Therefore, successive-approximation ADCs are inferior to flash ADCs in the sense of conversion speed due to the above adverse effect.
Multistage pipelined architectures divide the single analog-to-digital converter into two or more stages, in which all stages are operated concurrently and hence increase the throughput rate. A multistage pipelined ADC consists of two or more stages with the first stage that determines the most significant m bits and with the remaining N-m bits determined by the later stage(s). The first stage always works on the most recent sample, while the later stage(s) operate(s) on pass samples. Sample and hold circuits between individual stages allow the ADC to handle more than one samples at one time and thus the throughput rate increases.
Multistage pipelined ADCs consume less power and occupy less silicon area when compared to that of flash ADCs, because fewer comparators are required in pipelined converters than that of flash ADCs to obtain same resolution. However, multistage pipelined ADCs suffer from multistage gain error which arises from the non-ideal gain amplifiers between different stages.
Cyclic comparison ADC performs N-bit conversion through N stages. One of the bits in the length-N digital word is determined in each stage. FIG. 1 shows a block diagram of a prior art bit cell 100. Each bit cell corresponds to a single bit analog-to-digital conversion. The bit cell 100 includes a sample-and-hold (S/H) circuit 101, a single-bit ADC 102, a single-bit digital-to-analog converter (DAC) 103, a voltage subtractor 104, and an amplifier 105. The S/H circuit 101 samples an analog input signal IN. Then, the S/H circuit 101 provides the held analog signal VIN to the ADC 102 and the voltage subtractor 104. The ADC 102 receives a median voltage VREF of the dynamic range of the conversion, which is compared with the analog signal VIN to generate a single-bit digital signal DOUT. Then, the digital signal DOUT is passed to the single-bit DAC 103. The single-bit DAC 103 generates an analog signal V1 according to the digital output DOUT. V1 is then passed to the voltage subtractor 104. The voltage subtractor 104 subtracts the analog signal V1 from the analog input signal VIN and provides the amplifier 105 with the difference signal (i.e. VIN−V1). The amplifier 105 which has a gain of two that doubles the amplitude of the difference signal (VN−V1) to generate the analog output voltage OUT. The analog output voltage OUT is then passed to subsequent stage for conversion.
FIG. 2 shows a diagram illustrating an algorithm performed by the bit cell 100, and FIG. 3 shows a diagram illustrating the operation of the bit cell 100. The analog input signal VIN sourced externally or from previous bit cell is compared with the median voltage VREF of the conversion range (step 201) to generate a single-bit digital signal DOUT, where a “0” means VIN<VREF and a “1” means VIN Error! Objects cannot be created from editing field codes. VREF. The digital signal DOUT undergoes a mathematical operation of Error! Objects cannot be created from editing field codes. or Error! Objects cannot be created from editing field codes. (steps 202, 203). The operation result is transferred to next bit cell.
Cyclic comparison ADCs can be implemented with simple circuitry when compared to that of conventional successive-approximation ADCs, because identical reference is used in all stages. The simplification of circuitry reduces the requirements on power consumption and silicon area. Voltage-mode cyclic comparison ADCs are usually realized in switched-capacitor (SC) techniques, for which synchronization is critical. The time for N-bit conversion of voltage-mode cyclic comparison ADCs is limited to O(N) of clock cycles. However, the linearity of the SC cyclic comparison ADC depends on the linearity of capacitor and the accuracy in capacitor matching. The SC cyclic comparison ADCs also suffer from the adverse effects of common SC circuit, such as charge sharing, charge leakage, e.t.c. Despite the silicon area is reduced with circuitry simplification, the overall silicon area reduction is still limited by the capacitors.